A Formal HDL and its use in the FM

A synchronous, hierarchical, occurrence-oriented, hardware description language (HDL) has been formalized with the Boyer-Moore logic. Well-formed HDL circuits are recognized by a predicate, and a unit-clock simulator de nes the meaning of circuits expressed in the HDL. This HDL has been used to specify an implementation of the FM9001 microprocessor that has been mechanically proved to implement the FM9001 instruction-level speci cation. All proofs were mechanically checked using the Boyer-Moore theorem-proving system. The formalization of the HDL, the FM9001 user-level speci cation, and the FM9001 HDL implementation architecture speci cation required more than seven hundred function de nitions. The mechanical proof is composed of thousands of theorem prover proof requests and millions of theorem prover inference steps.